1. Technical Field
The present disclosure relates in general to the manufacture of semiconductor devices, and more particularly to novel processes for forming metal silicide contact pads on semiconductor devices.
2. Related Art
As technology in products and equipment continues to become more complex, the use of integrated circuit (IC) devices in these products and equipment is basically essential. In addition, consumers and manufacturers alike have continued to desire smaller product size, which requires a continued decrease in overall IC chip size. As a result, the large-scale integration of circuit components, such as transistors and capacitors, has become a necessity for decreased overall size, but increased device performance. Thus, semiconductor device improvements have been largely accomplished by reducing device feature size to the point where currently micron and sub-micron device features are being used, and predictions for future device sizes do not foresee an end to the trend of ever smaller and denser devices.
Along with desired reductions in device size, and thus increased chip densities, comes a required reduction in device power consumption that imposes the use of decreased device feature lengths. This is because, as a general rule, device speed varies inversely with device feature length, while power consumption increases approximately with the square of the device feature length. Thus, feature sizes currently being employed are in the micron and sub-micron or 0.13 um range, and it is expected that the device and feature sizes will continue to decrease in the future.
Metal silicide has been employed to provide the electrical contact between parts of the semiconductor devices and metal interconnects primarily because of the reduced contact resistance and sheet resistance provided by metal silicide. Self-Aligned metal silicide contact structures, commonly referred to as “salicide” structures, are often used to minimize contact resistance. In a conventional salicide process, for example, for the contact pads for a MOS transistor, source and drain regions are formed aligned to a gate electrode structure and/or any sidewall spacers that may be present. A blanket metal layer is deposited so that silicon, at the upper surface of source, drain and gate regions, is in contact with the metal. Examples of suitable metal silicide gate materials include, but are not limited to tungsten silicides, titanium silicides, cobalt silicides, and nickel silicides, and combinations thereof. The wafer is then heated (annealed) to a temperature to undergo a reaction and form a metal silicide. Dielectrics, such as the sidewall spacers when the silicide process if for a transistor, prevent silicide formation in undesired locations. When no silicon is available on a part of a device structure, no silicide forms thereon. After the metal silicide is formed, the unreacted metal is then removed, and regions of metal silicide are revealed. After removal of the metal not reacted to form a silicide, a second, higher temperature silicide anneal step is often employed to stabilize the silicide regions formed and to provide the lowest possible silicide resistivity.
In view of the above, while salicide formed on gates and source/drain regions reduces parasitic resistance, line width limitations challenge salicide implementation in smaller features and devices. One type of salicide that has proven particularly effective in such applications has been cobalt salicide, i.e., cobalt silicide formed by a self-aligning process. Cobalt is regarded as a useful material in self-aligned salicide processing because of its low resistance and its silicon-compatible lattice structure. However, cobalt and cobalt salicide (CoSiX), for example, in transistor applications, can penetrate into the junction area, resulting in junction leakage, increase in contact resistance, and deteriorating transistor current drive. Generally speaking, high temperatures are required for reacting cobalt and silicon, and a significant portion of the silicon substrate gets consumed in the process, causing the undesirable changes in the gate junction depth. Therefore, in conventional semiconductor manufacturing processes, cobalt salicide processing is typically only used in mid- and back-end processes to avoid process temperatures that are too high. In some applications, a titanium (Ti) or a titanium nitride (TiN) layer is formed on the cobalt layer prior to annealing in order to avoid cobalt oxidation.
However, the conventional process for depositing a Ti/TiN cap over the cobalt typically results in poor step coverage. More specifically, for example, looking at FIG. 1, which illustrates a semiconductor structure 100 having wordlines 110, 120 disposed on either side of a source/drain region 130, a convention deposition of a Ti/TiN cap 140 is shown deposited over a cobalt layer 150. With conventional processes, the cobalt 150 is deposited at generally equal thickness over both the wordlines 110, 120 as well as the source/drain region 130. However, in conventional processes, the Ti/TiN cap 140a deposition results in poor step coverage. More specifically, with such conventional processes is that the Ti/TiN cap layer 140 typically deposited on wordlines is too thick, usually as a consequence of trying to gain better step coverage over the source/drain region 130. Thus, as illustrated, although the Ti/TiN cap 140 thickness on the wordlines 110, 120 is high, the thickness of the Ti/TiN cap 140a over the source/drain region 130 is much lower in comparison. Consequently, the excess thickness of the Ti/TiN cap 140 over the wordlines 110, 120 tends to suppress cobalt silicide formation, and as a result the cobalt layer can exhibit thinning in certain areas on the wordline, which can result in an electrical open for that contact area even after the salicide process. Additionally, the insufficient thickness of the Ti/TiN cap 140a over the source/drain region 130 increases the possibility of agglomeration of the cobalt during the silicide process, which often results in leakage of the finished device.
Accordingly, in view of the above, it would be desirable to have new metal silicide formation processes for forming metal silicide contact pads on semiconductor device features, but that do not suffer from the deficiencies found in the conventional approaches.